1. Field of the Invention
This invention is related to the field of processors and, more particularly, to zero extension of instruction execution results within processors.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Such processors may benefit from the large body of software written to the x86 architecture (since such processors may execute the software and thus computer systems employing the processors may enjoy increased acceptance in the market due to the large amount of available software).
As computer systems have continued to evolve, 64 bit address size and operand size has become desirable. A larger address size allows for programs having a larger memory footprint (the amount of memory occupied by the instructions in the program and the data operated upon by the program) to operate within the memory space. A larger operand size allows for operating upon larger operands, or for more precision in operands. More powerful applications and/or operating systems may be possible using 64 bit address and/or operand sizes.
Unfortunately, the current x86 architecture is limited to a maximum 32 bit operand size and 32 bit address size. The operand size refers to the number of bits operated upon by the processor (e.g. the number of bits in a source or destination operand). The address size refers to the number of bits in an address generated by the processor. Thus, processors employing the x86 architecture may not serve the needs of applications which may benefit from 64 bit address or operand sizes.
An additional problem which may be encountered in attempting to provide a 64 bit operand size in an x86 compatible processor arises from the multiple operand sizes supported by the x86 architecture. More particularly, the current x86 architecture supports operand sizes of 8, 16, and 32 bits. Instructions having different operand sizes may be freely intermixed in a code sequence. Furthermore, the destinations of the instructions may be the same architected registers, even though the operand sizes are different. Thus, a first instruction having one operand size may update a register which provides a source operand for a second instruction having a different operand size. If the operand size of the second instruction is larger than the operand size of the first instruction, a definition of the source operand provided to the second instruction is needed. This problem is further compounded by the addition of a 64 bit operand size.